oneAPI DevSummit at IWOCL 2021

April 26, 2021

Join us for the first 2021 oneAPI Developer Summit at IWOCL focused on oneAPI and Data Parallel C++ for accelerated computing across xPU architectures (CPU, GPU, FPGA, and other accelerators). In this one-day virtual conference, you will hear from industry and academia speakers working on innovative cross-platform, multi-vendor architecture solutions developed on oneAPI. Learn from fellow developers and connect with other innovators. Please join us, a self-sustained, vibrant community to support each other using oneAPI and Data Parallel C++.

This event took place on April 26th, 2021.

Agenda

Schedule: April 26th

Schedule: April 26th

10:00 - 10:10

Presenting

10:10 – 10:50 AM CET VENDOR UPDATE

SYCL 2021 Vendor Update

VENDOR UPDATE SYCL 2021 Vendor Update Join us to hear the latest and greatest on SYCL support status and plans to learn about the latest on DPC++, SYCL, ComputeCpp, DPC++ for NVIDIA GPUs and hipSYCL. Hear the latest the following SYCL experts: Andrew Richards will cover DPC++ for NVIDIA GPUs and ComputeCpp; Ronan Keryell from Xilinx will speak on Khronos SYCL SPEC; James Reinders from…
Presenting

10:50 – 11:20 AM CET DEVCLOUD UPDATE

Developer tools to get you started on oneAPI

DEV CLOUD UPDATE Developer tools to get you started on oneAPI oneAPI compilers, programming tools, and performance libraries enable application development across XPUs free of the economic and technical challenges of heterogeneous parallelism. The Intel® DevCloud for oneAPI provides a sandbox to develop cross-architecture applications using the Intel® oneAPI Toolkits and Intel CPUs, GPUs, and FPGAs. DevCloud access is free for 120 days with extensions…
Presenting

11:20 – 12:50 AM CET HANDS-ON SESSION

Application optimization with Cache-aware Roofline Model and Intel oneAPI tools

HANDS-ON SESSION Application optimization with Cache-aware Roofline Model and Intel oneAPI tools In this tutorial, we will introduce the Cache-aware Roofline Model (CARM) and expose its basic principles when modelling the performance upper-bounds of Intel CPU and GPU devices. We will also showcase CARM implementation in Intel® Advisor and demonstrate how we can use it to drive the application optimization. For this purpose, we will…
Presenting

12:50 – 1:10 PM CET LUNCH

1:10 – 1:40 PM CET TECH TALK

AI > A Deep Dive into a Deep Learning Library for the A64FX Fugaku CPU – Meet the Developer

TECH TALK AI > A Deep Dive into a Deep Learning Library for the A64FX Fugaku CPU – Meet the Developer Kentaro Kawakami will share the development story to get oneAPI oneDNN on Arm for the A64FX Fugaku CPU. Fujitsu managed to make full use of Arm SVE architecture, and succeeded in improving performance by 9.2 times in training and 7.8 times in inference. Using…
Presenting

1:40 – 2:10 AM CET LIGHTNING TALK

Great Cross-Architecture Challenge Application Showcase

LIGHTNING TALK Great Cross-Architecture Challenge Application Showcase The Great Cross-Architecture Challenge was a 14-week contest intended for both professional and student software developers interested in developing cross-architecture applications using oneAPI. Participants were challenged to be the next “oneAPI hero” by either porting an existing C/C++ or CUDA application using the Intel(r) DPC++ Compatibility Tool or creating an entirely new oneAPI application. As part of the…
Presenting

2:10 – 2:40 PM CET KEYNOTE

SYCL 2020 in hipSYCL: DPC++ features on AMD GPUs, NVIDIA GPUs and CPUs

KEYNOTE SYCL 2020 in hipSYCL: DPC++ features on AMD GPUs, NVIDIA GPUs and CPUs HipSYCL is one of the four major SYCL implementations, with a particular focus on and aggregating hardware support for multivendor hardware provided by those toolchains within one single framework. Recently, hipSYCL has also started adopting DPC++/SYCL 2020 features such as unified shared memory, reductions and more in order to increase portability…
Presenting

2:40 - 3:00 PM CET LIGHTNING TALK

Bringing SYCL to Super Computers with Celerity

TECH TALK Bringing SYCL to Super Computers with Celerity In the face of ever-slowing single-thread performance growth for CPUs, the scientific and engineering communities increasingly turn to accelerator parallelization to tackle growing application workloads. Existing means of targeting distributed memory accelerator clusters impose severe programmability barriers and maintenance burdens. The Celerity programming environment seeks to enable developers to scale C++ applications to accelerator clusters with…
Presenting

3:00 – 3:10 PM CET BREAK

3:10 - 3:30 PM CET LIGHTNING TALK

Great Cross-Architecture Challenge Application Showcase

LIGHTNING TALK Great Cross-Architecture Challenge Application Showcase The Great Cross-Architecture Challenge was a 14-week contest intended for both professional and student software developers interested in developing cross-architecture applications using oneAPI. Participants were challenged to be the next “oneAPI hero” by either porting an existing C/C++ or CUDA application using the Intel(r) DPC++ Compatibility Tool or creating an entirely new oneAPI application. As part of the…
Presenting

3:30 – 4:00 PM CET TECH TALK

It’s Acceleration but Faster! A Business Perspective on FPGA Development.

TECH TALK It’s Acceleration but Faster! A Business Perspective on FPGA Development. The talk will explore the balance between time-to-market and performance optimization of FPGA application developments. Informed by Creative Solutions Space Ltd (CSS)’s journey from RTL to OpenCL to Intel’s OneAPI platform, the discussion focusses on real world examples and the advantages of using agile approaches to FPGA development.Creative Solutions Space Ltd (CSS)’s goal…
Presenting

4:00 – 4:30 PM CET TECH TALK

Migrating and tuning a CUDA-based stencil computation to DPC++

TECH TALK Migrating and tuning a CUDA-based stencil computation to DPC++​ Reverse Time Migration takes advantage of the finite-difference method (FD) to perform the numerical approximations for the acoustic wave equation. Stencil computation applied to this numerical method represents a computational bottleneck when developing RTM applications, and therefore needs to be optimized to guarantee timely results and efficiency when allocating resources for hydrocarbon exploration. This…
Presenting

4:30 - 4:45 PM CET BREAK

4:45 - 5:15 PM CET TECH TALK

Comparative Analysis of Intel HLS Design Tools on a Case Study in Neuromorphic

TECH TALK Comparative Analysis of Intel HLS Design Tools on a Case Study in Neuromorphic​ Academic computing clusters and cloud-based systems, such as Amazon Web Services and Google Cloud, have been integrating high-end FPGAs for high-performance computing (HPC) into their ecosystems, increasing the availability of FPGAs to a broader community. On these platforms, high-level synthesis (HLS) tools are featured to enable developers to describe FPGA…
Presenting

5:15 - 5:45 PM CET TECH TALK

TAU Performance System

TECH TALK TAU Performance System​ The TAU Performance System® [http://tau.uoregon.edu] supports profiling and tracing of programs written using the Intel OneAPI. Intel OneAPI provides two interfaces for programming – OpenCL and DPC++/SYCL for CPUs, GPUs, and other devices. TAU has been tested on Intel Gen12 GPUs now available in Intel TigerLake CPUs and DG1 cards using the Intel BaseKit and HPCToolkit software stacks from OneAPI.…
Presenting

5:45 - 6:00 CET Closing

Closing

Developer Summit at IWOCL 2021 Conclusion
Presenting

6:00 - 7:00 PM CET Happy Hour

HAPPY HOUR

We will Open the Happy hour with a fun Jeopardy game where you can answer some easy questions about oneAPI and DPC++ to win some fun prizes and DPC++ book. Then you will be get to some creative exercises to tap into your creative genius (https://thefreethoughtproject.com/study-children-brilliant-education-dumbs-down/) led by Sarah and Sujata. They will be leading the group through a few quick and fun exercises to…
Presenting
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