HIP on Aurora: Bringing HIP to oneAPI
Future DOE exascale system will be based on AMD (Frontier, El Capitan) or Intel (Aurora) hardware. HIP is thus a likely target for many Exascale applications, and HIP on Aurora ECP project’s objective is to bring portability to those application by offering HIP support on top of oneAPI. Derived from University of Finland’s HIPCL, our new HIP backend CHIP-SPV can target Intel GPUs through either Level Zero or OpenCL runtimes. To achieve this goal the HIPLZ project contributed the required changes to enable SPIR-V generation from HIP in LLVM/Clang14.
https://www.alcf.anl.gov/news/argonne-s-brice-videau-prepares-hip-applications-aurorahttps://github.com/CHIP-SPVhttps://clang.llvm.org/docs/UsersManual.html#spir-v-support
Speaker(s)
Brice Videau
Brice Videau is a computer scientist at Argonne National Laboratory’s Leadership Computing Facility, where his research focuses on heterogeneous programming models for HPC, performance optimization, and autotuning. Brice is also a member of the Khronos OpenCL working group.
