oneAPI Tools Panel
Speaker(s)
Paul Petersen
Paul Petersen is a Sr. Principal Engineer in IAGS (Intel Architecture, Graphics & Software), and oneAPI Tools Architect. He received a Ph.D. in Computer Science from the University of Illinois in 1993. Starting at Kuck and Associates, Inc. (KAI) projects included contributions to the auto-parallelizing compiler (KAP) and was involved in the early definition and implementations of OpenMP. While at KAI, he developed the Assure line of parallelization/correctness products, for Fortran, C++ and Java. In 2000, Intel Corporation acquired KAI, and he joined the software tools group creating the Thread Checker products, which evolved into the Inspector and Advisor components of the Intel® Parallel Studio. Inspector uses dynamic binary instrumentation to detect memory and concurrency bugs, and Advisor uses similar techniques along with performance measurement and modeling to assist developers in transforming existing serial applications to be ready for parallel execution. The focus on product architecture in Parallel Studio XE and its component product architecture transitioned to creating and leading a pathfinding team. The work on defining next generation features for parallel runtimes and software analysis tools to better enable Intel platforms, more recently transitioned to current role leading the oneAPI Tools Architecture team.
Ruyman Reyes
Ruyman is a software engineer with background in High Performance Computing and extensive experience in programming models and heterogeneous platforms. Ruyman holds a PhD from University of La Laguna (Spain). He completed his dissertation, named Directive based approach to Heterogeneous Computing in December 2012, while working as Application Developer in the Edinburgh Parallel Computing Center (EPCC). He moved later in December 2013 to Codeplay Software where he has helped to define the SYCL open standard for heterogeneous programming, led development of ComputeCpp and more recently contributions to the DPC++ compiler project.
Ramesh Peri
Ramesh is a senior Principal Engineer in IAGS and is the performance architect of oneAPI. His area of expertise includes programming languages, compilers, debuggers, and profilers for Intel datacenter/accelerator/HPC/mobile/IoT platforms. He developed software development tools for number of processors that include machine learning accelerators, DSPs, micro-controllers, GPUs and a variety of application processors based on many different kinds of architectures like x86 and ARM. He holds a Ph.D in computer science from the University of Virginia(USA), an MTech from IIT Kanpur (India), and a BS from REC Warangal (India). Prior to Intel, Ramesh worked at Hewlett Packard, Lucent and Panasonic.
Xiaozhu Meng
Xiaozhu is an active developer for the Rice HPCToolkit. He is presently working on an implementation of the HPCToolkit on top of the Level 0 in oneAPI and have designed and implemented a parallel binary analysis for analyzing program control flow using OpenMP task parallelism and Intel® oneAPI Threading Building Blocks (TBB).