DPC++ and C/C++/Fortran OpenMP Compilers for CPUs and Xe Accelerators
In the high-performance computing realm, the emerging DPC++/SYCL programming model is getting attention while OpenMP* continues to be the popular parallel programming model to a wide range of HPC/AI accelerators such as Xe GPUs and FPGAs. This presentation includes:
- A brief overview of the DPC++ and OpenMP offloading Models
- An overview of Intel’s LLVM compiler technology for DPC++ and OpenMP offloading
- A deep dive on performance tuning for one AI workload on Intel CPU and Xe GPU
Speaker(s)
Xinmin Tian
Xinmin Tian is a Senior Principal Engineer and Compiler Architect at Intel Corporation and serves as Intel’s representative on OpenMP Architecture Review Board (ARB) and OpenMP C/C++ subcommittee chair. He drives OpenMP offloading, vectorization and parallelization compiler technologies for current and future Intel architectures. His current focus is on DPC++ compiler optimizations for oneAPI Toolkits, LLVM-based OpenMP offloading, and tuning HPC/AI application performance on Intel® CPUs and Xe accelerators. He has a Ph.D. in Computer Science, holds 27 U.S. patents, has published over 60 technical papers with over 1200 citations of his work, and has co-authored three books that span his expertise.
